谨言by来自远方7鲤鱼乡:DFF

来源:百度文库 编辑:九乡新闻网 时间:2024/07/07 14:06:25
In order to make the flip-flops and other memory elements needed, we employ a little bit of positive feedback.

Here is a high-level schematic of a simple D-flip-flop:


The boxes with the lines in the center are called "transmission gates."They are composed of one PMOS and one NMOS in parallel. Notice thatthe inverted vesion of every signal that goes to transmission gate hasthe inverted version as well. That is because one is needed for thePMOS and the other for the NMOS.

There are two distiguishable states, "transparent" and "opaque." In thetransparent state, the drains and sources are electrically connected.In the opaque state, the drains are elecrically issolated from thesources.

The end result is that the D input passes to the output when the CLKsignal transitions from high to low. At all other times, there arepositive feedback mechanisms that keep the output at the value it waslast.

Please see if you can see this function from the confuguration.
Hint:The flip-flop is actually composed of two "latches." Each with itsown set of tranmission gates and and feedback loop that are opaque ortransparent based on the level of the clock.