蹋踏的区别:Comparing SOI and bulk FinFETs: Performance, manufacturing variability, and cost - Solid State Technology

Comparing SOI and bulk FinFETs: Performance, manufacturing variability, and cost
 
 
Executive OVERVIEW
This article compares the performance, process variability, and cost of speculative FinFET process flows based on SOI and bulk silicon substrates. While both SOI and bulk FinFETs should be able to achieve comparable performance, a bulk FinFET fabrication flow will require more process complexity. In SOI wafers, the buried oxide layer isolates individual transistors, while in bulk devices, isolation must be created by the wafer process. We show that, because the bulk FinFET process is more complex, it will lead to 140-160% more device variability, and thus to significant manufacturing and process control challenges. Though SOI substrates are more expensive, the costs of the more complex bulk FinFET process largely offset this expense, resulting in a roughly equivalent cost basis with bulk at production volumes.
 
 
Horacio Mendez, SOI Industry Consortium, Austin, Texas, USA; David M. Fried, IBM, East Fishkill, NY USA; Srikanth B. Samavedam, Freescale Semiconductor, East Fishkill, NY USA; Thomas Hoffmann, IMEC, Leuven, Belgium; Bich-Yen Nguyen, Soitec,Austin, Texas, USA
 
Asthe semiconductor industry looks toward the 22nm technology node, somemanufacturers are considering a transition from planar CMOS transistorsto the three-dimensional (3D) FinFET device architecture. Relative toplanar transistors, FinFETs offer improved channel control and,therefore, reduced short channel effects. While the gate in a planartransistor sits above the channel, the gate of a FinFET wraps around thechannel, providing electrostatic control from both sides.
 
Challenges of a 3D structure
 
The3D structure introduces new parasitic capacitances and new criticaldimensions that must be controlled to optimize performance. The gatelength in a FinFET is measured parallel to the length of the fin, whilethe gate width is the sum of twice the fin height plus the fin width.Fin height limits the drive current and the gate capacitance, while finthickness affects threshold voltage and short channel control, as wellas contributing to second order metrics such as power consumption.
 
Ina 22nm node device, fin width might be on the order of 10-15nm. Finheight would ideally be twice that or more—increasing the fin heightincreases the transistor density, allowing more effective gate width tofit in a smaller planar footprint. As we will discuss, however, tallerfins make both the fin etch and, for bulk FinFETs, the recess etch andisolation implant more difficult.
 
Controlled manufacturingof a 3D structure with such small features presents new process controlchallenges. The trench etch that creates the fins must maintain avertical profile with minimal sidewall roughness over a 2:1 or greateraspect ratio. Variability and yield are important considerations asmanufacturers decide which process flow to adopt.
 
Thisarticle analyzes the performance, variability, and cost of two potentialFinFET process flows—one based on silicon-on-insulator (SOI)substrates, and one using bulk silicon substrates with an implantedjunction for fin isolation.
 
SOI-based flow.The SOI-based flow is the most straightforward. The fin etch simplystops on the wafer's buried oxide layer; the fin height is defined bythe initial SOI layer thickness. Moreover, because of the buried oxidelayer, adjacent fins are fully isolated from each other and noadditional isolation steps are required. In the fully-depleted,undoped-channel devices being considered for this node, only gatefabrication and source/drain implants are needed to complete the device.
 
 

Figure 1. Process flow for bulk FinFET with junction isolation.
 
 
Bulk silicon-based flow.In contrast, when a bulk silicon substrate is used, there is no cleardemarcation of the base of the fin, and no inherent isolation layer.Instead, the process must manufacture transistor isolation. In ajunction-isolated flow (Fig. 1), the fin etch isfollowed by an oxide fill step. The oxide deposition must fill a deep,high aspect ratio trench, without voids or other defects. Polishing theoxide back to the silicon sets the fin height, then a recess etch clearsthe space between fins. This recess etch, like the initial trench etch,has no obvious stop layer—etch depth depends on etch time, and issubject to microloading effects as the fin density varies through thedesign space. Though the oxide provides insulation between adjacentfins, the transistors are still connected underneath the oxide. Ahigh-dose angled implant at the base of the fin creates a dopantjunction and completes the isolation.
 
 

Figure 2. Process flow for bulk FinFET with material isolation.
 
 
Material-isolated flow. Some research has also considered a material-isolated flow (Fig. 2),in which a hard mask spacer protects the sides of the fin while oxideis allowed to grow from the oxide trench isolation across the bottom ofthe fin. In this process, the degree of oxide growth depends on thegrowth time—all fins must have the same thickness to ensure completeisolation. The oxide isolation growth process is inherently difficult tocontrol, and the flow adds several process steps relative to thejunction-isolated flow. Because of its complexity, we do not believethat the material isolation approach will be viable for manufacturing,and have not included this flow in subsequent analyses.
 
SOI and bulk flows offer matched performance
 
Relativeto DC performance, SOI and bulk-based FinFETs achieve comparable on/offcurrent ratios for matched device dimensions [1]. Differences begin toappear when considering such parameters as junction leakage andparasitic capacitance. Here, the oxide ground plane intrinsic to SOImakes the 22nm node's performance targets more achievable.
 
As described above, isolation in junction-isolated FinFETs is provided by a high-dose (1018/cm3)dopant layer at the base of the fin. This layer can be implanted eitherbefore or after the recess oxide deposition and etch; however,alignment between the junction and the oxide layer is critical. Itsimpact on device performance is similar to that of spacer-channelalignment in planar transistors.
 
Performing the implantbefore the recess oxide deposition and etch would amplify the impact ofnon-uniformities in the already challenging recess etch step. Instead,most process flows being considered for commercialization perform theoxide deposition and etch first, using the oxide layer to align thejunction implant. Even in this process order, optimizing implantconditions to provide appropriate dopant junctions at the base of thefin is quite challenging.
 
 

Figure 3. Transistor matching for SOI-based FinFETs, bulk silicon-based FinFETs, and planar transistors [2].
 
 
Implantsproduce a dopant gradient, even under the best circumstances. It'sdifficult to implant sufficient dopant at the base of the fin producing agradient in the body of the fin. While SOI and bulk FinFETs can achievecomparable leakage performance, random dopant fluctuations in the bulkFinFET will affect transistor-matching characteristics (Fig. 3). SOI-based devices have no junction isolation implant, and so are not subject to this effect.
 
Thedifferences between junction isolation and SOIs buried oxide alsoaffect parasitic capacitances. Because of their design, all FinFETs aremore prone to parasitic effects than comparable planar devices [3]. Theburied oxide layer helps minimize capacitance for SOI devices, whilejunction-isolated bulk devices suffer from the capacitance due to thejunction. As fin height increases, however, the total capacitanceincreases and the contribution of junction capacitance becomes lessdominant. For fin height greater than 40-50nm, junction capacitanceimposes a 5-6% ring oscillator penalty.
 
Reducing variability
 
Thoughcandidate processes can be identified based on performanceconsiderations, the "best" process might vary significantly depending onthe design. A high-performance design might be less concerned aboutoverall cost, and more concerned about variability and variabilityreduction. A low-power commodity chip might be most concerned aboutleakage and power consumption,but might be extremely cost-sensitive.Rather than attempt toaddress these issues, our analysis focuses on thevariability andcost of a simplified generic process.
 
From acost and variability standpoint, our model can be seen as a best case:it considers only digital circuit elements, with a single thresholdvoltage. It assumes only one fin pitch—a probable scenario, asmanufacturers are likely to adjust transistor dimensions by adding finsto a given device. Using a single fin pitch simplifies lithography andetch—an important consideration as both processes are likely to bechallenging at the 22nm node.
 
More realistic devices arelikely to see additional costs and increases in the number of processsteps. Additional threshold voltages will add implant masks, whileadditional metal layers will bring more metal deposition, patterning,and polishing steps. We hope readers will be able to evaluate their ownprocesses within the framework we provide.
 

 
Forthe variability analysis, we assumed that SOI and bulksilicon-basedFinFETs will use similar toolsets. We don't expect the SOI trench etchto achieve tighter tolerances than the equivalent bulk process step, forinstance. We also assumed that process improvements over time willbenefit both toolsets equally.
 

 
Theadditional process steps required for bulk FinFETs, however, impose asubstantial variability penalty. In the SOI-based flow (Table 1),the most important sources of variability are the substrate itself(which defines fin height) and the fin etch verticality and sidewallquality. Bulk FinFETs (Table 2) suffer from fin etchvariability as well. In fact, the need for additional oxide isolationmeans that fins must maintain their vertical profiles with even higheraspect ratios. Moreover, neither the fin etch nor the recess oxide etchcan depend on an intrinsic stop layer comparable to that provided by anSOI wafer's buried oxide. These are timed etches, with all thevulnerability to process variation and microloading effects thatimplies. Finally, as discussed above, controlling the junction isolationimplant is likely to be extremely difficult.
 

 
Not only are the bulk FinFET process steps likely to be more highly variable, but there are numerically more of them. As Table 3shows, our model SOI flow requires 56 process steps, while thejunction-isolated bulk flow requires 91, including two additional masklayers. Even if all the steps were equally variable, bulk FinFETs wouldface more process variability. In our model, we expect bulk FinFETs tosee 140-160% of the variability of SOI-based devices (Table 4).
 

 
Theadditional process steps impose a similar burden on process cost (Table3). We estimate that by 2012, the cost of SOI substrates will fall to$500, due to increasing use of these substrates in volume manufacturing.Though SOI substrates will remain more expensive than bulk siliconwafers, their contribution to the total process cost decreases as thetotal cost per wafer increases. Even for our model flow, the net costincrease for SOI FinFETs is only $136 per wafer. For more realisticprocesses, we expect the cost difference between bulk and SOI to bewithin the margin of error of this study (Fig. 4).
 
 

Figure 4. Total cost difference between SOI and bulk FinFETs, relative to totalwafer cost.
 
 
Conclusion
 
Thisstudy evaluates performance, variability and cost differences betweenFinFETs fabricated with junction isolation on bulk silicon wafers, andFinFETs fabricated on SOI wafers. Our analysis shows that bulk and SOIwafers are, for all practical purposes, equivalent in performance andcost; however, bulk-based FinFETs are much more challenging tomanufacture due to increased process variability. The higher variabilityassociated with bulk wafers can lead to end product unpredictability.We found that the two process schemes delivered comparable DC and ACperformance. Junction-isolated FinFETs do suffer from a small increase(5-6%) in parasitic capacitance.
 
In contrast, processvariability comparisons show that SOI FinFETs are likely to havesuperior matching characteristics.Fin height and width are likely to bemore easily controlled inthe SOI process, while the bulk process facessignificantmanufacturing and process control challenges.
 
Atthe 22nm technology node, density scaling expectations are such thatFinFETs begin to offer tangible advantages over planar technology.
 
First,contacted gate pitch must shrink to a point of constraining gate lengthbelow any channel length demonstrated for high-performance transistors.The inherent short-channel advantages of FinFET may allow this scaling,without the deleterious effects of massive channel doping required byplanar devices.
 
Also, SRAM bitcell area expectations havebegun to dictate variability requirements of the individual transistors. Undoped-body FinFETs, as has been the focus of most research, wouldremove the random dopant fluctuation (RDF) component of devicevariability. This reduction may be essential for achieving low operatingvoltages in high-performance SRAM bitcells.
 
SOI-basedFinFETs suffer a modest cost penalty, due to the increased substratecost. At high volumes, this is largely offset by the cost of the morecomplex bulk process.
 
References
 
 
1.B. Parvais, et. al., "The Device Architecture Dilemma for CMOSTechnologies: Opportunities and Challenges of FinFET Over PlanarMOSFET," 16th Intl. Symp. on VLSI Tech., Systems, and Applications,Hsinchu, Taiwan, 2009,(VLSI-TSA 2009).
 
2. T. Hoffman,"Perspectives on Technological Opportunities & Challenges ofMulti-Gate Non-Planar Device Architectures," Intl. Workshop on INSIGHTin Semi. Dev. Fabrication, Metrology, and Modeling, Napa, CA,2009,(Insight 2009).
 
3. M. Guillorn et al., "FinFETPerformance Advantage at 22nm: An ACperspective," Symp. on VLSI Tech.,Digest of Tech. Papers, pp. 12-13, 2009, (VLSI-2009).
 
 
Biography
 
Horacio Mendezreceived his Bachelors degrees in mechanical engineering and materialsscience and Masters in semiconductor physics from the U. of Texas, andis executive director at the SOI Industry Consortium, 1010 Land CreekCove, Austin, TX 78746 USA; 512-992 1809; hmendez@soiconsortium.org